Continuing the Sirius Legacy
An emulation of the Sirius handheld and AlephOS 2.0, with notes on the challenges of working with its 1-bit display.
Interactive Hardware Emulation
More than two decades after its original development in Lahore, surviving source code, firmware, and engineering records have been used to reconstruct parts of the Sirius system in emulation. The original Keil C51 source code, disassemblies, and binary images were reconstructed to run in cycle-accurate emulation across three concurrent 8051 processor cores clocked at 40 MHz, including the timing of communication between the processors and the dual-controller liquid-crystal display.
Enter AlephOS 2.0
Operate the reconstructed Sirius directly in its own responsive exhibit view. The display, softkeys, keyboard, and hardware timing remain together on one page that scales to the screen in front of you.
Launch the live emulator- Processors
- 3 × AT89C51RD2
- Clock
- 40 MHz each
- Display
- 128 × 64 KS0108 LCD
- Controls
- F1–F6 · keyboard · arrows
Delivering Text and Graphics on a 1-Bit Low-Resolution Display
Most modern interfaces rely on color, hardware compositing, and antialiased text. Designing for the Sirius meant operating within a set of practical limits imposed by a monochrome reflective STN liquid-crystal panel measuring 128×64 pixels. The display contained 8,192 pixels and used 1,024 bytes of video memory.
Because the display was small, the software had to use the available pixels carefully. The engineering challenges extended from physical silicon characteristics to optical and typographic constraints:
- The Dual-Die Controller Boundary: The Samsung KS0108 display is divided between two controller chips, each driving a 64×64 column domain. The left half is selected by asserting
CS1; the right half by assertingCS2. Drawing a continuous horizontal line, window title, or text string across the display’s center column (x=63 to x=64) requires switching chip-select lines mid-stream, splitting byte writes across two distinct address counters. - Vertical Page Architecture: Video RAM in the KS0108 is organized not in linear horizontal scanlines, but in eight vertical “pages” (Page 0 through Page 7), each 8 pixels high. Writing a single byte affects an 8-pixel vertical column. Consequently, drawing diagonal lines or blitting proportional characters across arbitrary y-coordinates requires expensive read-modify-write bit shifts: reading the existing page byte, masking the bitfield, ORing the glyph slice, and writing it back.
- Read Latency & Character Pre-Subtraction: The KS0108 silicon has a hardware read latency: an initial read command merely latches the byte under the internal address counter into an output register, advancing the pointer. A second read cycle is required to actually sample the latched pixel data. In firmware, the glyph blitter (
LcdPutchar) performs two reads before writing and never re-addresses, necessitating a strict mathematical pre-subtraction of two columns from every character coordinate to prevent severe horizontal displacement artifacts. - Micro-Typography & Information Density: Legible text at 64 vertical pixels requires microscopic glyphs that preserve character recognition without colliding into widget borders. Sirius uses a strict typographic hierarchy: an ultra-compact 3×5 proportional micro font (
FONT_TINY) for softkey labels and buttons with mandatory 1-pixel borders and 2-pixel margins; a 5×7 system font for menu entries and dialogs; a 10×16 numeral font for the scientific calculator; and custom proportional bitmap fonts for rendering Urdu text in Arabic Naskh script. - Atkinson Error Diffusion for Continuous Imagery: Rendering technical schematics and photographs on a pure 1-bit panel without hardware grayscale required algorithmic error diffusion. Standard Bayer ordered dithering produced distracting geometric cross-hatching, while standard Floyd-Steinberg error diffusion muddied sharp mechanical borders. Sirius adopted Atkinson dithering (pioneered at Apple), which diffuses only three-quarters (75%) of the quantization error across neighbouring pixels, discarding the rest. This preserves clean, glowing highlight whites and sharp contrast on reflective liquid crystal displays.
- Slow STN Liquid Crystal Response: Passive-matrix Super Twisted Nematic (STN) panels suffer from relatively slow pixel relaxation times. Full-screen redraws or rapid dark/light inversions produce noticeable ghosting and contrast degradation. The AlephOS display coprocessor was engineered to execute dirty-rectangle blitting, redrawing only modified bounding boxes rather than wiping the entire 1,024-byte display plane.
Explore the Silicon & PCB Architecture
For a detailed breakdown of the tri-microcontroller bus interconnect, clock distributions at 40 MHz, full electrical specifications, and PCB architectural block diagrams: